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Senior PD Engineer

ExperiencedNo visa sponsorship
Capgemini logo

at Capgemini

Consultancies

Posted 7 days ago

No clicks

**Senior Physical Design Engineer** leads complex 10nm chip designs at CAPGEMINI. Duties span from full chip/block level Physical Design - floorplanning, partitioning, power mesh, clock tree, placement, CTS, place and route - to timing analysis, ECO tasks, validation, and SI/EM/DRC/LVS checks. Expertise required: 8+ years in RTL2GDSII on advanced nodes, proficiency in Synopsys/Cadence CAD tools, synthesis and DFT knowledge, Python/Perl scripting, sign-off closure skills. Drive multiple high-complexity design cycles, collaborate globally.

Compensation
Not specified

Currency: Not specified

City
Not specified
Country
Romania

Full Job Description

About CAPGEMINI:

Are you in search for a new challenge? Are you equipped with forward thinking spirit and experienced in digital design flows and tools? Physical Design has a multi-lateral spectrum of increasing complexity which involves deep understanding of cutting-edge designs and technologies, methods, tools, development and implementation flows.

Take the opportunity and join us as a Senior Physical Design Engineer!

Your Role:

Your role:

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);

In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;

Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);

In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;

Be part of the overall Low Power solution development and implementation;

Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);

Complete multiple design cycles of high complexity with little supervision.

Desired qualifications/skills:

8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k 1million+ instances in designs;

Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence

Good knowledge of synthesis flow, insertDFT scan/coverage and optimization

Excellent floorplan, power plan, CTS, place, route, and timing closure skills;

Proficiency using Perl/TCL/Python scripting and Makefile;

Expertise in timing STA/PTSI signal integrity closure, ECO generation/implementation skill;

Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;

Experience with sign-off tape-out closure work;

Any top level floor planning, pin assignment tape out activities is a plus.

What Will You Love About Working Here:

  • Collaborative and Inclusive Culture: Youll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.
  • Flexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;
  • Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.

Capgemini Romania is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.

About CAPGEMINI:

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.

Senior PD Engineer

Compensation

Not specified

City: Not specified

Country: Romania

Capgemini logo
Consultancies

7 days ago

No clicks

at Capgemini

ExperiencedNo visa sponsorship

**Senior Physical Design Engineer** leads complex 10nm chip designs at CAPGEMINI. Duties span from full chip/block level Physical Design - floorplanning, partitioning, power mesh, clock tree, placement, CTS, place and route - to timing analysis, ECO tasks, validation, and SI/EM/DRC/LVS checks. Expertise required: 8+ years in RTL2GDSII on advanced nodes, proficiency in Synopsys/Cadence CAD tools, synthesis and DFT knowledge, Python/Perl scripting, sign-off closure skills. Drive multiple high-complexity design cycles, collaborate globally.

Full Job Description

About CAPGEMINI:

Are you in search for a new challenge? Are you equipped with forward thinking spirit and experienced in digital design flows and tools? Physical Design has a multi-lateral spectrum of increasing complexity which involves deep understanding of cutting-edge designs and technologies, methods, tools, development and implementation flows.

Take the opportunity and join us as a Senior Physical Design Engineer!

Your Role:

Your role:

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);

In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;

Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);

In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;

Be part of the overall Low Power solution development and implementation;

Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);

Complete multiple design cycles of high complexity with little supervision.

Desired qualifications/skills:

8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k 1million+ instances in designs;

Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence

Good knowledge of synthesis flow, insertDFT scan/coverage and optimization

Excellent floorplan, power plan, CTS, place, route, and timing closure skills;

Proficiency using Perl/TCL/Python scripting and Makefile;

Expertise in timing STA/PTSI signal integrity closure, ECO generation/implementation skill;

Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;

Experience with sign-off tape-out closure work;

Any top level floor planning, pin assignment tape out activities is a plus.

What Will You Love About Working Here:

  • Collaborative and Inclusive Culture: Youll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.
  • Flexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;
  • Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.

Capgemini Romania is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.

About CAPGEMINI:

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.