at UBS
Bulge Bracket Investment BanksPosted 25 days ago
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**Payment Risk Specialist**: Leverage FPGA design and C++ to orchestrate real-time trading rules. Architect cycle-accurate FPGA layouts, network interfaces up to 100GbE, and drive full design flow. Implement lock-free data structures and optimize network performance. Collaborate globally with IT, Quant teams, and Traders. Provide Level 3 production support. 3+ years of FPGA/C++/Linux experience required.
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Full Job Description
| Join a high-performance team building ultra-low latency trading systems where nanoseconds matter. Youll design and implement a trading rules engine for real-time controls using a hybrid of FPGA hardware and high-performance C++, enabling deterministic execution and rapid interaction with the markets. Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) or C++. Architect cycle-accurate FPGA designs and high-speed network interfaces (10/25/40/100GbE, RoCEv2) is preferred. Build simulation and verification frameworks for FPGA reliability. Drive full FPGA design flow (synthesis, place & route, timing closure). Interface C++ applications with FPGA hardware for real-time orchestration. Implement lock-free data structures and concurrency control in Linux. Build low-latency network apps using kernel bypass (e.g., Rivermax). Analyze system performance and resolve latency bottlenecks. Collaborate with global IT, Quants, and Traders across asset classes. Provide Level 3 support for production systems. | Show more APAC Algo Trading Low Latency C++ Developer |
