What Youll Be Doing

• Lead Functional Specification Development for advanced digital systems
• Design and implement Microarchitecture (uArch) for high-performance blocks
• Perform RTL Debugging, ensuring design correctness and efficiency
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks
• Collaborate with verification, physical design, and architecture teams
• (Bonus) Contribute to Front-End Synthesis and optimization
• (Nice to have) Experience working on SoC-level integration and design
• (Nice to have) Apply Power Optimization Techniques for energy-efficient designs

What You Bring:

• 7+ years of hands-on experience in digital design
• Strong knowledge of Verilog and/or VHDL
• Familiarity with SystemVerilog is a plus
• Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus
• Proven experience in RTL design, uArch development, and functional specs
• Deep understanding of linting tools, CDC methodologies, and debugging flows
• Familiarity with synthesis tools and SoC design is a strong plus
• Bachelors degree in EE, ECE, CE, CS, or a related field required
• MS or PhD highly desired
• Excellent communication and collaboration skills

Why Youll Love Working With Us

• Work on innovative semiconductor products with real-world impact
• Join a collaborative, forward-thinking engineering team
• Enjoy a flexible work environment and competitive compensation
• Opportunities for technical leadership and career growth